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rt9173/a 1 ds9173/a-18 march 2007 www.richtek.com features z z z z z support both ddr 1 (1.25v tt ) and ddr 2 (0.9v tt ) requirements z z z z z sop-8, to-252-5 and to-263-5 packages z z z z z capable of sourcing and sinking 3a peak current z z z z z current-limiting protection z z z z z thermal protection z z z z z integrated power mosfets z z z z z generates termination voltages for sstl-2 z z z z z high accuracy output voltage at full-load z z z z z adjustable v out by external resistors z z z z z minimum external components z z z z z shutdown for standby or suspend mode operation with high-impedance output z z z z z rohs compliant and 100% lead (pb)-free pin configurations applications z ddr memory termination z active termination buses z supply splitter peak 3a bus termination regulator ordering information general description the rt9173/a regulator is designed to convert voltage supplies ranging from 1.6v to 6v into a desired output voltage which adjusted by two external voltage divider resistors. the regulator is capable of sourcing or sinking up to 3a of peak current while regulatin g an output voltage to within 2% (ddr 1) and 3% (ddr 2) or less. the rt9173/a, used in conjunction with series termination resistors, provides an excellent voltage source for active termination schemes of high speed transmission lines as those seen in high speed memory buses and distributed backplane designs. the voltage output of the regulator can be used as a termination voltage for ddr sdram. current limits in both sourcing and sinking mode, plus on- chip thermal shutdown make the circuit tolerant of the output fault conditions. (top view) to-263-5 (rt9173a) 4 2 3 5 1 vout refen vcntl (tab) gnd vin to-252-5 (rt9173a) 4 2 3 5 1 vout refen vcntl (tab) gnd vin 2 3 4 5 8 7 6 vcntl vin gnd refen vout vcntl vcntl vcntl sop-8 (rt9173) note : richtek pb-free and green products are : ` rohs compliant and compatible with the current require- ments of ipc/jedec j-std-020. ` suitable for use in snpb or pb-free soldering processes. ` 100%matte tin (sn) plating. rt9173/a package type m5 : to-263-5 l5 : to-252-5 s : sop-8 operating temperature range p : pb free with commercial standard g : green (halogen free with commer- cial standard) 3a sink & source 1.5a sink & source
rt9173/a 2 ds9173/a-18 march 2007 www.richtek.com typical application circuit vin refen gnd vcntl vout rt9173/a en 2n7002 r 1 r 2 c ss v in = 2.5v v cntl = 3.3v c cntl c in r tt c out r dummy r 1 = r 2 = 100k , r tt = 50 / 33 / 25 c out(min) = 10 f (ceramic) + 1000 f under the worst case testing condition r dummy = 1k as for vout discharge when vin is not present but vcntl is present c ss = 1 f, c in = 470 f (low esr), c cntl = 47 f test circuit vin refen gnd vcntl vout rt9173/a 2.5v 3.3v 1.25v c out i l v out v vin refen gnd vcntl vout rt9173/a 2.5v 3.3v 1.25v c out v out v r l 1.25v 0v r l and c out time deleay 0.2v a figure 1. output voltage tolerance, v load figure 2. current in shutdown mode, i shdn
rt9173/a 3 ds9173/a-18 march 2007 www.richtek.com vin refen gnd vcntl vout rt9173/a 2.5v 3.3v c out v out v r l 1.25v 0v r l and c out time deleay 1.25v 0.2v v out v refen v out would be low if v refen < 0.2v v out would be high if v refen > 0.8v vin refen gnd vcntl vout rt9173/a 2.5v 3.3v 1.25v c out i l v out v a power supply with current limit vin refen gnd vcntl vout rt9173/a 2.5v 3.3v 1.25v c out i l v out v a figure 3. current limit for high side, i limit figure 4. current limit for low side, i limit figure 5. refen pin shutdown threshold, v trigger
rt9173/a 4 ds9173/a-18 march 2007 www.richtek.com functional pin description pin name pin function vin power input voltage gnd ground vcntl gate drive voltage refen reference voltage input and chip enable vout output voltage function block diagram cntl current limiting sensor thermal vcntl vin gnd vout refen
rt9173/a 5 ds9173/a-18 march 2007 www.richtek.com absolute maximum ratings z input v oltage ------------------------------------------------------------------------------------------------------------ 7v z power dissipation ----------------------------------------------------------------------------------------------------- internall y limited z esd rating ------------------------------------------------------------------------------------------------------------- 2kv z storage temperature range ---------------------------------------------------------------------------------------- ? 65 c to 150 c z lead temperature (soldering, 10 se c.) --------------------------------------------------------------------------- 260 c z power dissipation, p d @ t a = 25 c to-263-5 ----------------------------------------------------------------------------------------------------------------- 1.923w to-252-5 ----------------------------------------------------------------------------------------------------------------- 1.471w sop-8 -------------------------------------------------------------------------------------------------------------------- 0.625w z package thermal resistance (note 3) to-263-5, jc ---------------------------------------------------------------------------------------------------------- 7.7 c/w to-252-5, jc ---------------------------------------------------------------------------------------------------------- 8 c/w sop-8, jc -------------------------------------------------------------------------------------------------------------- 23.2 c /w to-263-5, ja ------------------------------------------------------------------------------------------------------------ 52 c/w to-252-5, ja ----------------------------------------------------------------------------------------------------------- 68 c/w sop-8, ja -------------------------------------------------------------------------------------------------------------- 160 c/w electrical characteristics (v in = 2.5v, v cntl = 3.3v, v refen = 1.25v, c out = 10 f (ceramic), t a = 25 c, unless otherwise specified.) parameter symbol test conditions min typ max units output offset voltage v os i out = 0a, figure 1 (note 1) -20 0 20 mv i l : 0a 1.5a, figure 1 -- 0.8/1.2 2/3 load regulation (ddr 1/2) v load i l : 0a -1.5a -- 0.8/1.2 2/3 % v in 1.6 2.5/1.8 -- input voltage range (ddr 1/2) (note 2) v cntl keep v cntl v in on operation power on and power off sequences -- 3.3 6 v operating current of vcntl i cntl no load -- 6.5 10 ma current in shutdown mode i shdn v refen < 0.2v, r l = 180 , figure 2 -- 50 90 a short circuit protection current limit i limit figure 3,4 3.0 -- -- a over temperature protection thermal shutdown temperature t sd 3.3v v cntl 5v 125 150 -- c thermal shutdown hysteresis guaranteed by design -- 50 -- c shutdown function v trigger output = high, figure 5 0.8 -- -- shutdown threshold trigger v trigger output = low, figure 5 -- -- 0.2 v note 1. v os offset is the voltage measurement defined as v out subtracted from v refen . note 2. for safely operate your system, the 3.3v rail must be tied to v cntl rather than 5v rail, especially for the new part of rt9173acl5. note 3. ja is measured in the natural convection at t a = 25 c on a low effective thermal conductivity test board (single layers, 1s) of jedec 51-3 thermal measurement standard. the case point of jc is on the on the center of v ctrl pins (lead 6 & 7) for sop-8 packages, the center of heat sink (tab) for to-252-5 and to-263-5 packages.
rt9173/a 6 ds9173/a-18 march 2007 www.richtek.com typical operating characteristics turn-on threshold vs. temperature 400 450 500 550 600 650 700 -40-20 0 20406080100120 temperature threshold voltage (mv) ( c) v cntl = 3.3v v in = 2.5v 1.25v tt @ 1.5a transient response time (250us/div) output transient voltage (mv) output current (a) 0 -50 50 100 0 1 2 -1 -2 v in = 2.5v v refen = v cntl = 3.3v swing frequency = 1khz 1.25v tt @ 3a transient response time (250us/div) output transient voltage (mv) output current (a) 0 -50 50 100 0 2 4 -2 -4 v in = 2.5v v refen = v cntl = 3.3v swing frequency = 1khz ( c) turn-on threshold vs. temperature 400 450 500 550 600 650 700 -40-20 0 20406080100120 temperature threshold voltage (mv) ( c) v cntl = 5.0v v in = 2.5v sourcing current (peak) vs. temperature 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 -40 -20 0 20 40 60 80 100 120 temperature sourcing current (a) ( c) v cntl = 3.3v v in = 2.5v v out = 1.25v sinking current (peak) vs. temperature 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 -40 -20 0 20 40 60 80 100 120 temperature sinking current (a) a v cntl = 3.3v v in = 2.5v v out = 1.25v
rt9173/a 7 ds9173/a-18 march 2007 www.richtek.com 0.9v tt @ 1.5a transient response time (250us/div) output transient voltage (mv) output current (a) 0 -50 50 100 0 1 2 -1 -2 v in = 1.8v v refen = 0.9v v cntl = 3.3v swing frequency = 1khz 0.9v tt @ 3a transient response time (250us/div) output transient voltage (mv) output current (a) 0 -50 50 100 0 2 4 -2 -4 v in = 1.8v v refen = 0.9v v cntl = 3.3v swing frequency = 1khz r ds(on) vs. temperature 0.22 0.23 0.24 0.25 0.26 0.27 0.28 0.29 0.30 0.31 25 35 45 55 65 75 85 95 105 115 125 temperature r ds(on) ( c) v cntl = 3.3v v refen = 1.0v v in = 0.9v v in = 0.8v v in = 0.85v () r ds(on) vs. temperature 0.23 0.24 0.25 0.26 0.27 0.28 0.29 0.30 0.31 0.32 25 35 45 55 65 75 85 95 105 115 125 temperature r ds(on) ( c) v cntl = 5.0v v refen = 1.0v v in = 0.9v v in = 0.8v v in = 0.85v () output short-circuit protection time (5ms/div) output short circuit (a) 8 6 10 12 0 2 4 -2 -4 v in = 2.5v v cntl = 3.3v v refen = 1.25v source force the output shorted to ground output short-circuit protection time (5ms/div) output short circuit (a) 8 6 10 12 0 2 4 -2 -4 v in = 2.5v v cntl = 3.3v v refen = 1.25v sink force the output shorted to v ddq
rt9173/a 8 ds9173/a-18 march 2007 www.richtek.com application information internal parasitic diode avoid forward-bias internal parasitic diode, v out to v cnt l , and v out to v in , the v out should not be forced some voltage respect to ground on this pin while the v cntl or v in is disappeared. consideration while designs the resistance of voltage divider make sure the sinking current capa bility of pull-down nmos if the lower resistance was chosen so that the voltage on v refen is below 0.2v. in addition, the capacitor and voltage divider form the low- pass filter. there are two reasons doing this design; one is for output voltage soft-start while another is for noise immunity. how to reduce power dissipation on notebook pc or the dual channel ddr sdram application? in notebook application, using richtek's patent " distributed bus terminator topology " with choosing richtek's product is encouraged. r0 r9 r8 r7 r6 r5 r4 r3 r2 r1 rn rn+1 rt9173/a rt9173/a vout vout refen bus(0) bus(1) bus(2) bus(3) bus(4) bus(5) bus(6) bus(7) bus(8) bus(9) bus(n) bus(n+1) terminator resistor distributed bus terminating topology figure 6 thermal consideration rt9173/a regulators have internal thermal limiting circuitry designed to protect the device during overload conditions. for continued operation, do not exceed absolute maximum operation junction temperature 125 c. the power dissipation definition in device is : p d = (v in - v out ) x i out + v in x i q the maximum power dissipation depends on the thermal resistance of ic package, pcb layout, the rate of surroundings airflow and temperature difference between junction to ambient. the maximum power dissipation can be calculated by following formula : p d(max) = ( t j(max) -t a ) / ja where t j(max) is the maximum operation junction temperature 125 c, t a is the ambient temperature and the ja is the junction to ambient thermal resistance. the junction to ambient thermal resistance ja highly depends on ic package, pcb layout, and the rate of surroundings airflow. ja for sop-8 package is 160 c/w and to-263-5 package is 52 c/w on standard jedec 51-3 ( single layer , 1s ) thermal test board. the maximum power dissipation at t a = 25 c can be calculated by following formula : p d(max) = (125 c - 25 c) / (160 c/w)= 0.625w (sop-8 package) p d(max) = (125 c- 25 c) / (52 c/w)= 1.923w (to- 263- 5 package ) since the multiple v ctrl pins of the sop-8 package are internally fused and connected to lead frame, it is efficient to dissipate the heat by adding cooper area on v ctrl footprint. figure 7 shows the package sectional drawing of sop-8. every package has several thermal dissipation paths, as show in figure 8, the thermal resistance equivalent circuit of sop-8. the path 2 is the main path of thermal flow due to these materials thermal conductivity. we define the center of multiple v ctrl pins are the case point of the path 2.
rt9173/a 9 ds9173/a-18 march 2007 www.richtek.com figure 7. the package section drawing of rt9173/a sop-8 package figure 8. thermal resistance equivalent circuit of rt9173/a sop-8 package the thermal resistance ja of ic package is determined by the package design and the pcb design. however, the package design has been decided. if possible, it's useful to increase thermal performance by the pcb design. the thermal resistance can be decreased efficiently by adding copper under the main path of thermal flow on the package. the maximum power dissipation depends on operating ambient temperature for fixed t j(max) and thermal resistance ja . for rt9173/a package, the figure 9 and the figure 10 show the thermal resistance ja vs. copper area of sop-8 and to-263-5 packages on single layer (1s) and 4-layer (2s2p) thermal test board at t a = 25 c, pcb copper thickness = 2oz. figure 10. thermal resistance ja vs. copper area of to-263-5 packages for example, as shown in figure 9, rt9173/a sop-8 with 10mm x 10mm cooper area on 4-layers (2s2p) thermal test board at t a = 25 c, we can obtain the lower thermal resistance about 45 c/w. the power maximum dissipation can be calculated as : p d(max) = (125 c - 25 c) / (45 c/w) = 2.22w (sop-8) as shown in figure 10, rt9173/a to-263-5 with 15mm x 15mm cooper area on 4-layers (2s2p) thermal test board at t a = 25 c, we can obtain the lower thermal resistance about 29 c/w. the power maximum dissipation ambient molding compound gold wire lead frame die pad die die pad molding compound lead frame case point junction r die r die-attach r die-pad r gold-line r lead frame r pcb r pcb ambient r molding-compound path 1 path 2 path 3 r lead frame internally fused ja vs. copper area 30 40 50 60 70 80 90 100 0 102030405060708090100 copper area (mm 2 ) ja (c/w) sop-8 2s2p thermal test board figure 9. thermal resistance ja vs. copper area of sop-8 packages thermal resistance vs. cooper area 0 10 20 30 40 50 60 70 0 50 100 150 200 250 300 350 400 cooper area (mm 2 ) thermal resistance (c/w) to-263-5 1s thermal test board 2s2p thermal test board
rt9173/a 10 ds9173/a-18 march 2007 www.richtek.com figure 11. power dissipation vs. copper area of sop-8 package figure 12. power dissipation vs. copper area of to-263-5 package can be calculated as : p d(max) = (125 c - 25 c) / (29 c/w) = 3.45w (to-263-5) figure 11 and figure 12 of power dissipation vs. copper area allow the designer to see the effect of rising ambient temperature on the maximum power allowed. cooper area vs. power dissipation 0 50 100 150 200 250 300 350 400 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 power dissipation (w) cooper area (mm 2 ) t a = 65 c t a = 55 c t a = 25 c to-263-5 2s2p thermal test board power dissipation vs. copper area 0 10 20 30 40 50 60 70 80 90 100 00.511.522.53 power dissipation (w) copper area (mm 2 ) t a = 65 c t a = 55 c t a = 25 c 2s2p thermal test board sop-8
rt9173/a 11 ds9173/a-18 march 2007 www.richtek.com dimensions in millimeters dimensions in inches symbol min max min max d 9.652 10.668 0.380 0.420 b 1.143 1.676 0.045 0.066 e 8.128 9.652 0.320 0.380 a 4.064 4.826 0.160 0.190 c 1.143 1.397 0.045 0.055 u 6.223 ref. 0.245 ref. v 7.620 ref. 0.300 ref. l1 14.605 15.875 0.575 0.625 l2 2.286 2.794 0.090 0.110 b 0.660 0.914 0.026 0.036 b2 0.305 0.584 0.012 0.023 e 1.524 1.829 0.060 0.072 5-lead to-263 plastic surface mount package outline dimension c b2 a b e v u d e l1 b l2
rt9173/a 12 ds9173/a-18 march 2007 www.richtek.com 5-lead to-252 surface mount package dimensions in millimeters dimensions in inches symbol min max min max a 2.184 2.388 0.086 0.094 b 0.381 0.889 0.015 0.035 b3 4.953 5.461 0.195 0.215 c2 0.457 0.889 0.018 0.035 d 5.334 6.223 0.210 0.245 e 6.350 6.731 0.250 0.265 h 9.000 10.414 0.354 0.410 l 0.508 1.780 0.020 0.070 l2 0.508 ref. 0.020 ref. l3 0.889 2.032 0.035 0.080 p 1.270 ref. 0.050 ref. v 5.200 ref. 0.205 ref. r 0.200 1.500 0.008 0.059 s 2.500 3.400 0.098 0.134 t 0.500 0.850 0.020 0.033 e p h l l2 c2 a l3 d b b3 r t s v
rt9173/a 13 ds9173/a-18 march 2007 www.richtek.com richtek technology corporation headquarter 5f, no. 20, taiyuen street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 fax: (8863)5526611 richtek technology corporation taipei office (marketing) 8f, no. 137, lane 235, paochiao road, hsintien city taipei county, taiwan, r.o.c. tel: (8862)89191466 fax: (8862)89191465 email: marketing@richtek.com a b j f h m c d i 8-lead sop plastic package dimensions in millimeters dimensions in inches symbol min max min max a 4.801 5.004 0.189 0.197 b 3.810 3.988 0.150 0.157 c 1.346 1.753 0.053 0.069 d 0.330 0.508 0.013 0.020 f 1.194 1.346 0.047 0.053 h 0.170 0.254 0.007 0.010 i 0.050 0.254 0.002 0.010 j 5.791 6.200 0.228 0.244 m 0.400 1.270 0.016 0.050

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